The invention relates generally to memory cells and more particularly of the type of memory cells employing a floating gate. This type of memory cell is a field effect transistor having source and drain regions connected by a channel region, a floating gate insulated from the channel and closely adjacent thereto, and a control gate insulated from and closely adjacent to the floating gate. As understood in the art by applying a suitable voltage between the control gate and the source or drain of the transistor, a charge may be trapped upon the floating gate which is insulated from the remainder of the structure. This charge influences the current which may be drawn through the underlying channel and permits by suitable means a determination of whether a charge is stored upon the floating gate or not. The floating gate may be discharged for example by a suitable voltage, of opposite polarity. Operation of the control gate with voltages less than those required to change the state of charge of the floating gate may be employed to determine whether there is a charge trapped upon the floating gate or not. Thus, such memories may be used as read-only memories, but the memories are erasable, so that they are known by the somewhat incongruous name of erasable or programmable read-only memories. In the manufacture of memories of the type using floating gate memory cells, it is desirable to pack as many cells as possible on the surface of the substrate.
One of the prior art floating gate memory cells is exemplified by U.S. Pat. No. 3,984,822 issued Oct. 5, 1976 to Simko et al. The patent describes a memory cell in which the floating gate is, as described in the art, self-aligned with respect to the source and drain. The term implies that the margins of the floating gate are used as a mask to determine the extent of the source and drain on the surface of the underlying substrate.
An erasable read only memory product employs cells of a type somewhat similar to those described in the above-identified patent except that in the product also the floating gate in the direction transverse to the source to the drain direction extended beyond the channel region of the transistor over the field oxide, namely, looking at the center section of the device, beyond the channel region in the direction at right angles to the source to drain direction.